Semiconductor devices, especially those that pertain to computer and telecommunications applications, have continued to be a focus for enhancing performance. Both smaller device size and higher speed of operation are performance targets. The success of many technology areas is dependent on the availability of high quality and cost effective integrated circuits. Transistors have been continually reduced in size as the ability to construct smaller gate structures has improved. As the size of transistors has decreased, the size of other components has become a limiting factor in increasing overall component densities.
Semiconductor devices employ a large number of openings in their design and manufacture. The size of these openings has been decreasing due to the demand for higher device packing densities and therefore smaller device size. As the size of the openings decreases, the need increases for tighter control to assure proper device operation and therefore overall quality. Some of these openings are typically used to provide electrical contacts.
A key area controlling the overall quality and reliability of semiconductor devices is the area of interconnections between the various integrated components and circuits of the device. As is well known, vias are metal filled openings between the various layers of a semiconductor device that provide electrical connection between the layers at appropriate points. Trenches contain metal runners that are positioned in a layer to electrically interconnect appropriate points in the layer including vias. As the size of the openings decrease, accurate positioning of the holes for vias and the trenches for runners are more difficult to construct.
Current construction techniques for stacked vias typically use a small “landing pad” to assure that appropriate connections are aligned and made from layer to layer. The landing pads are larger than the diameter of the via holes to allow for some degree of misalignment and still accomplish a reliable electrical connection. Metal runners may be narrower in width than the landing pads. Thus, if the trench areas are exposed correctly in the photolithography process, the landing pad areas tend to be underexposed. In contrast, if the landing pad areas are exposed correctly, the trench areas are usually overexposed. However, even if the landing pads and the trenches are the same width, the landing pads may be underexposed because generally they are much shorter. This disparate exposure effect creates the possibility of shorts across the landing pads and the runners.
To obviate the affects attributable to this disparate exposure effect, the industry has moved to biasing the reticle (photolithography mask), commonly using what is termed an optical proximity correction (OPC) technique. By biasing the landing pad features larger on the reticle, the exposure required for proper sizing of the trenches allows the landing pad areas to receive adequate exposure for the size needed, while at the same time adequately exposing the runner or trench areas. This solution, however, requires that spacing on the reticle be increased between openings and the runners or trenches, usually by a fixed margin or amount. As overall semiconductor device component size requirements continue to shrink, this fixed margin tends to become a limiting factor to minimizing component spacings.
Accordingly, what is needed in the art is a way to enhance the alignment process associated with the construction of vias and trenches without sacrificing critical space on the semiconductor wafer.